/proc/cpuinfo
• processor 条目包括这一逻辑处理器的唯一标识符。
• physical id 条目包括每个物理封装的唯一标识符。
• core id 条目保存每个内核的唯一标识符。
• siblings 条目列出了位于相同物理封装中的逻辑处理器的数量。
• cpu cores 条目包含位于相同物理封装中的内核数量。
• 如果处理器为英特尔处理器,则 vendor id 条目中的字符串是 GenuineIntel。
The following is an output from /proc/cpuinfo on a laptop with a Core 2 Duo T7200 CPU.
processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 CPU T7200 @ 2.00GHz
stepping : 6
cpu MHz : 1000.000
cache size : 4096 KB
physical id : 0
siblings : 2
core id : 1
cpu cores : 2
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe lm constant_tsc pni monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr lahf_lm
bogomips : 3990.09
clflush size : 64
As you can see, the file tells us we have one processor with two cores. Furthermore the cpu is clocked down to 1000 MHz. We also have a bunch of flags which tells us what extra instructions this processor has to offer.
flags
The flags line tells us what extra instructions the processor has to offer. This is a listing of flags with a short explanation of each. There is an even shorter explanation in the file /usr/include/asm/cpufeature.h.
Intel flags (This table is currently identical with /usr/include/asm/cpufeature.h. Hopefully some hardware god will share his wisdom and expand this table. )
Flag Description Common in processor types
• fpu Onboard (x87) Floating Point Unit
• vme Virtual Mode Extension
• de Debugging Extensions
• pse Page Size Extensions
• tsc Time Stamp Counter: support for RDTSC and WRTSC instructions
• msr Model-Specific Registers
• pae Physical Address Extensions: ability to access 64GB of memory; only 4GB can be accessed at a time though
• mce Machine Check Architecture
• cx8 CMPXCHG8 instruction
• apic Onboard Advanced Programmable Interrupt Controller
• sep Sysenter/Sysexit Instructions; SYSENTER is used for jumps to kernel memory during system calls, and SYSEXIT is used for jumps back to the user code
• mtrr Memory Type Range Registers
• pge Page Global Enable
• mca Machine Check Architecture
• cmov CMOV instruction
• pat Page Attribute Table
• pse36 36-bit Page Size Extensions: allows to map 4 MB pages into the first 64GB RAM, used with PSE.
• pn Processor Serial-Number; only available on Pentium 3
• clflush CLFLUSH instruction
• dtes Debug Trace Store
• acpi ACPI via MSR
• mmx MultiMedia Extension
• fxsr FXSAVE and FXSTOR instructions
• sse Streaming SIMD Extensions. Single instruction multiple data. Lets you do a bunch of the same operation on different pieces of input in a single clock tick.
• sse2 Streaming SIMD Extensions-2. More of the same.
• selfsnoop CPU self snoop
• acc Automatic Clock Control
• IA64 IA-64 processor Itanium.
• ht HyperThreading. Introduces an imaginary second processor that doesn’t do much but lets you run threads in the same process a bit quicker.
• nx No Execute bit. Prevents arbitrary code running via buffer overflows.
• pni Prescott New Instructions aka. SSE3
• vmx Intel Vanderpool hardware virtualization technology
• svm AMD “Pacifica” hardware virtualization technology
• lm “Long Mode,” which means the chip supports the AMD64 instruction set
• tm “Thermal Monitor” Thermal throttling with IDLE instructions. Usually hardware controlled in response to CPU temperature.
• tm2 “Thermal Monitor 2″ Decrease speed by reducing multipler and vcore.
• est “Enhanced SpeedStep”
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